1. Field of the Invention
The present invention relates to an apparatus for parallel addition of two binary data values to obtain an intermediate processing result, such as addition of two floating-point mantissas or addition of two partial processing values obtained during a multiplication or division operation executed upon two floating-point mantissas, and for executing round-off processing of that intermediate result.
In particular, the invention relates to such an addition apparatus which also includes a capability for detecting an appropriate one of a plurality of possible bit position at which round-off is to be executed within the intermediate processing result.
2. Description of the Prior Art
When two floating-point number mantissas are added together, or when two intermediate results of certain floating-point arithmetic operations are added together, e.g. adding together two partial products to obtain the intermediate product which is to be subjected to round-off processing, in the case of a multiplication operation, there may be a plurality of different possible positions at which round-off processing of the result of that addition can be executed. For example, when two 25-bit floating-point values each having the normalized format designated by numeral 10 in FIG. 1 (i.e. *.** . . . *, where * denotes an arbitrary "0" or "1" bit state) are added together, then an intermediate sum will be obtained having the format designated by numeral 11, i.e. XX.XX . . . XX. If a carry up from the bit 24 position has occurred as a result of the addition, then the leading bit (bit 25) of the addition result will be "1", i.e. the sum format will be as indicated by numeral 16. In that case, assuming that there are only two possible round-off positions, the position designated by 15 will be selected as the round-off position, where "1" will be added to execute round-off. After round-off has been executed, the most significant 25 bits of the result will be outputted as the final sum, designated by numeral 18, by a right-shift operation. If no carry up has occurred, then the leading bit of the result will be "0", and the sum format will be as indicated by numeral 12. In that case, the round-off position will be the bit 0 position (LSB), and the 25 bits extending from and including bit 0 of the result obtained from the round-off processing will then be outputted as the final sum result, after any necessary left-shifting has been executed if required to normalize the result.
In the following, a bit position in an intermediate processing result which corresponds to the LSB position in a normalized floating-point mantissa (such as the value designated as 10 in FIG. 1) will be referred to as the normalized LSB position, since there may be bits of lower significance than that position in such an intermediate result.
Similar considerations apply when two partial processing results of a multiplication or division operation are added together, e.g. when two final partial products are added together to obtain an intermediate product, which is then subjected to round-off processing, followed by a shift operation if necessary.
With the round-off method described above there are two possible round-off bit positions, determined in accordance with the state of the MSB of the addition result. However with another method, there are three positions, which are determined in accordance with a combination of states of the two leading bits of the intermediate sum.
In the prior art it has been necessary to use one addition circuit for parallel addition of the two input values or partial products, then to detect the state of the MSB (or the two leading bits) in the intermediate sum or intermediate product that results from the addition, then to use another addition circuit as a round-off adder, with the round-off bit position being determined in accordance with the detected MSB state, or combination of states of the two leading bits of the intermediate sum or intermediate product. Thus, a significant amount of time is required to execute round-off processing, while in addition a separate addition circuit is required to execute round-off.